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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-08 02:52:53 +02:00
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b3e2001e1f094eccf925f0b9e88b3d7cae5e5cb0
yosys/tests/arch
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Marcelina Kościelnicka 15b0d717ed iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
..
anlogic
memory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 22:42:03 +02:00
common
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
ecp5
abc9: replace cell type/parameters if derived type already processed (#2991)
2021-09-09 10:05:55 -07:00
efinix
tests: Centralize test collection and Makefile generation
2020-09-21 15:07:02 +02:00
gowin
Gowin: deal with active-low tristate (#2971)
2021-08-20 21:21:06 +02:00
ice40
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.
2021-08-11 14:52:38 +02:00
intel_alm
memory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 22:42:03 +02:00
machxo2
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
nexus
memory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 22:42:03 +02:00
quicklogic
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
xilinx
FfData: some refactoring.
2021-10-07 04:24:06 +02:00
run-test.sh
Add default assignments to SB_LUT4
2021-04-20 12:46:21 +02:00
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