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luke
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yosys
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b3d6b277ea63fc9da4a728f5e0a34a2e38ebdf5f
yosys
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techlibs
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gowin
T
History
Clifford Wolf
e9d73d2ee0
Indenting fixes in gowin sim cell lib
2016-11-08 18:54:00 +01:00
..
cells_map.v
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
cells_sim.v
Indenting fixes in gowin sim cell lib
2016-11-08 18:54:00 +01:00
Makefile.inc
Added initial version of "synth_gowin"
2016-11-01 11:31:13 +01:00
synth_gowin.cc
Added hex constant support to write_verilog
2016-11-03 12:13:23 +01:00