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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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b3b9f1bf2effdecbb8a1a334aa637fccedb211e8
yosys/passes
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Alberto Gonzalez 76dfa81790 cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
..
cmds
splitnets: Clean up pseudo-private member usage
2020-06-13 05:47:55 +00:00
equiv
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
fsm
fsm_extract: avoid calling log_signal to determine wire name
2020-06-08 03:49:58 +02:00
hierarchy
Merge pull request #2089 from rswarbrick/modports
2020-06-08 15:48:11 +02:00
memory
Add flooring division operator
2020-05-28 22:59:04 +02:00
opt
Do not optimize away FFs in "prep" and Verific fron-end
2020-06-09 15:54:14 +02:00
pmgen
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
2020-04-22 17:43:25 -07:00
proc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
sat
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
techmap
msvc does not support designated initializers in structs
2020-06-17 16:20:52 +02:00
tests
Add flooring division operator
2020-05-28 22:59:04 +02:00
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