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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 11:35:20 +02:00
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yosys/passes
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Miodrag Milanović 51b210c93c Merge pull request #5600 from YosysHQ/fix_musllinux
musllinux fix so wheels build can work
2026-01-13 07:08:04 +01:00
..
cmds
Check for missing port in SDC code
2026-01-10 04:00:17 +00:00
equiv
Merge pull request #5357 from rocallahan/builtin-ff
2025-09-17 11:37:16 +02:00
fsm
fsm_detect: add adff detection
2025-11-06 23:29:47 +02:00
hierarchy
hierarchy.cc: Tidying
2025-10-15 09:42:47 +13:00
memory
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
opt
Parallelize opt_merge.
2026-01-08 04:21:39 +00:00
pmgen
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
proc
proc_clean: Removing an empty full_case is doing something
2026-01-07 13:10:32 +13:00
sat
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
techmap
Merge pull request #5600 from YosysHQ/fix_musllinux
2026-01-13 07:08:04 +01:00
tests
test_cell.cc: Generate .aag for all compatible cells
2025-12-02 14:03:36 +13:00
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