yosys/tests/arch at b20bb653ce0bfe452f8a1ff4a7a9b64262acced3 - yosys - Gitea: Git with a cup of tea

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Pepijn de Vos c2d358484f Gowin: deal with active-low tristate (#2971 )

* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests

2021-08-20 21:21:06 +02:00

..

memory_bram: Reuse extract_rdff helper for make_outreg.

2021-05-25 22:42:03 +02:00

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.

2021-08-11 14:52:38 +02:00

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

Gowin: deal with active-low tristate (#2971 )

2021-08-20 21:21:06 +02:00

test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.

2021-08-11 14:52:38 +02:00

memory_bram: Reuse extract_rdff helper for make_outreg.

2021-05-25 22:42:03 +02:00

machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

2021-02-23 17:39:58 +01:00

memory_bram: Reuse extract_rdff helper for make_outreg.

2021-05-25 22:42:03 +02:00

quicklogic: ABC9 synthesis

2021-04-17 20:54:58 +02:00

ast: Use better parameter serialization for paramod names.

2021-03-18 00:52:00 +01:00

run-test.sh

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00