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https://github.com/YosysHQ/yosys.git
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Daniel M'BOUYOU
25c7053114
#6130 fixed arith_tree so that a chain link narrower than its consumer is left out of the tree, and added an equivalence regression for the exact failing shape. Cover what that test does not: structural checks that the narrow link survives as its own cell, on both the raw $add path and the alumacc $alu path, and a mixed case where a wider chain consuming the truncated link as a leaf still folds and stays equivalent. Signed-off-by: Daniel M'BOUYOU <[email protected]>
212 lines
3.8 KiB
Plaintext
212 lines
3.8 KiB
Plaintext
read_verilog <<EOT
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module equiv_add3(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add5(
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input [3:0] a, b, c, d, e,
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output [3:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_add8(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_mixed(
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input [1:0] a,
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input [3:0] b,
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input [5:0] c,
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output [5:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_3op(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a - b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_mixed(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_sub_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_double_neg(
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input [3:0] a, b, c,
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output [4:0] y
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);
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wire [3:0] ab = a - b;
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assign y = c - ab;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -reset
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# A chain link that is narrower than the cell consuming it truncates its own
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# result, and that truncation is observable in the wider consumer. Flattening
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# the chain must not recover the carry the narrower link discarded.
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read_verilog <<EOT
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module equiv_narrow_intermediate(
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input [7:0] a, b, c,
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output [8:0] y
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);
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wire [7:0] t = a + b;
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assign y = t + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -reset
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# Only the truncating link must be excluded: with a truncated t entering the
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# wider (t+c+d) chain as a leaf, the wide part still folds into a tree and the
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# whole result stays equivalent.
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read_verilog <<EOT
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module equiv_trunc_mixed(
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input [7:0] a, b, c, d,
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output [9:0] y
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);
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wire [7:0] t = a + b;
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assign y = t + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt -assert arith_tree
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design -load postopt
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select -assert-min 1 t:$fa
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design -reset
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