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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 18:24:48 +02:00
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b1569de5377ee72de12abf2f234ea46ce91adfbb
yosys/passes
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History
Martin Povišer 4c3203866f exec: Add missing newline
2024-08-07 13:02:00 +02:00
..
cmds
exec: Add missing newline
2024-08-07 13:02:00 +02:00
equiv
equiv_simple: Take FFs into account for driver map
2024-02-21 12:05:52 +01:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
memory
memory_map: Explain -iattr better
2024-03-06 15:15:37 +01:00
opt
Merge pull request #4176 from povik/opt_expr-performance
2024-07-15 16:10:25 +02:00
pmgen
Merge pull request #4474 from tony-min-1/mchp
2024-07-29 15:28:44 +02:00
proc
proc_rom: Set src on the emitted memory
2024-07-25 23:14:27 +01:00
sat
Set ranges on exported wires in VCD and FST
2024-08-02 15:23:00 +02:00
techmap
cellmatch: add comments
2024-05-03 16:42:41 +02:00
tests
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
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