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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 09:58:22 +02:00
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b13e6bd375dc19fc2d6a3e67cdc6c045da732200
yosys/techlibs/intel
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Clifford Wolf 9ac560f5d3 Add "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <[email protected]>
2018-01-09 18:42:19 +01:00
..
a10gx
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
common
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
cyclone10
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
cycloneiv
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
cycloneive
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
cyclonev
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
max10
Clean whitespace and permissions in techlibs/intel
2017-10-05 16:23:49 +02:00
Makefile.inc
Initial Cyclone 10 support
2017-11-08 22:45:21 -06:00
synth_intel.cc
Add "dffinit -highlow" and fix synth_intel
2018-01-09 18:42:19 +01:00
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