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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 11:18:31 +02:00
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b13e6bd375dc19fc2d6a3e67cdc6c045da732200
yosys/passes
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Clifford Wolf eb67a7532b Add $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <[email protected]>
2018-02-23 13:14:47 +01:00
..
cmds
Recognize stand-alone obj pattern even when it contains a slash
2018-02-13 14:55:24 +01:00
equiv
Improve log messages in equiv_make
2018-01-19 16:20:40 +01:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Bugfix in hierarchy blackbox module port width handling
2018-01-07 16:35:22 +01:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Add $allconst and $allseq cell types
2018-02-23 13:14:47 +01:00
proc
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
sat
Fix a bug in clk2fflogic memory handling
2017-12-14 03:05:55 +01:00
techmap
Add "dffinit -highlow" and fix synth_intel
2018-01-09 18:42:19 +01:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
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