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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 19:19:48 +02:00
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b111ea12286b45e51fc453e3f4d7ac906e1a9f7c
yosys/techlibs
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Tim 'mithro' Ansell b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
2018-10-08 16:52:12 -07:00
..
achronix
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
common
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
coolrunner2
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
easic
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ecp5
ecp5: Don't map ROMs to DRAM
2018-10-01 18:34:41 +01:00
gowin
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
greenpak4
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ice40
Add iCE40 SB_SPRAM256KA simulation model
2018-09-10 11:57:24 +02:00
intel
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
xilinx
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
2018-10-08 16:52:12 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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