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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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af840bbc63a9a82a9c4e2c24476c70659efee63f
yosys/techlibs
T
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Eddie Hung af840bbc63 Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
..
achronix
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
anlogic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
common
Merge pull request #772 from whitequark/synth_lut
2019-01-02 15:44:57 +01:00
coolrunner2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
easic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ecp5
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
gowin
Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master
2019-04-22 09:09:27 +02:00
greenpak4
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ice40
ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments
2019-04-21 21:40:11 +01:00
intel
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
sf2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
xilinx
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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