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luke
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yosys
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adb483ddfd
yosys
/
frontends
History
Vamsi K Vytla
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
..
aiger
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
ast
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ilang
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-04-27 09:44:24 -07:00
json
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
liberty
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
rpc
ast, rpc: record original name of $paramod\* as \hdlname attribute.
2020-04-18 03:47:28 +00:00
verific
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
verilog
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00