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luke
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yosys
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ac808c5e2aa0fbcfb5b56160131fcc61ba13da05
yosys
/
backends
/
edif
T
History
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
...
Signed-off-by: Clifford Wolf <
[email protected]
>
2019-04-18 17:45:47 +02:00
..
edif.cc
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
Makefile.inc
Added edif backend (still under construction)
2013-08-22 11:34:55 +02:00
runtest.py
Add generation of logic cells to EDIF back-end runtest.py
2017-03-19 14:57:40 +01:00
