This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-01 02:27:34 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
aba8639a3fbc2e5f4ff0ffd18aac98a97ba6ae75
yosys
/
techlibs
T
History
Clifford Wolf
a860efa8ac
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
blackbox.sed
initial import
2013-01-05 11:13:26 +01:00
Makefile.inc
Added EXTRA_TARGETS Makefile variable
2013-03-28 16:53:40 +01:00
simlib.v
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
stdcells_sim.v
initial import
2013-01-05 11:13:26 +01:00
stdcells.v
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00