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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 23:48:53 +02:00
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ab4b9e8db481cd24b61cc0dc14bb5bf74d08006d
yosys/backends
T
History
N. Engelhardt ab4b9e8db4 smt: handle failure of setrlimit syscall
2019-07-15 23:33:18 +08:00
..
aiger
Rename __builtin_bswap32 -> bswap32
2019-07-09 09:35:09 -07:00
blif
Fix handling of offset and upto module ports in write_blif, fixes #1040
2019-05-25 17:45:14 +02:00
btor
Merge origin/master
2019-06-27 11:20:15 -07:00
edif
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
firrtl
Fix static shift operands, neg result type, minor formatting
2019-05-21 13:04:56 -07:00
ilang
Allow attributes on individual switch cases in RTLIL.
2019-07-08 11:34:58 +00:00
intersynth
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
json
Fix json formatting
2019-06-21 20:01:40 +02:00
protobuf
Support filename rewrite in backends
2019-06-18 14:39:52 -07:00
simplec
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
smt2
smt: handle failure of setrlimit syscall
2019-07-15 23:33:18 +08:00
smv
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
spice
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
2019-07-11 07:25:52 +02:00
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