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luke/yosys
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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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ab3f6266ad732e0fc3e02e2addc0c5486293702a
yosys/tests
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Clifford Wolf ab3f6266ad Use "abc -dff" in "make test"
2013-12-31 21:25:34 +01:00
..
asicworld
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
2013-05-24 15:15:59 +02:00
hana
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
i2c_bench
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
k68_vltor
Now only use value from "initial" when no matching "always" block is found
2013-03-31 11:51:12 +02:00
simple
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
tools
Use "abc -dff" in "make test"
2013-12-31 21:25:34 +01:00
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