yosys/techlibs/xilinx at aae5f2ca0873d3a2a96f51d70b3b5bc2f2d0bcf9 - yosys - Gitea: Git with a cup of tea

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Clifford Wolf 8520b7fbe0 Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

..

Added Xilinx example for Basys3 board

2015-02-01 17:09:34 +01:00

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

.gitignore

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

arith_map.v

Various cleanups in xilinx techlib

2015-01-18 19:43:54 +01:00

brams_bb.v

Added Xilinx bram black-box modules

2015-04-06 08:44:30 +02:00

brams_init.py

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

brams_map.v

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

brams.txt

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

cells_map.v

Various cleanups in xilinx techlib

2015-01-18 19:43:54 +01:00

cells_sim.v

Disabled (unused) Xilinx tristate buffers

2015-02-04 16:33:59 +01:00

Makefile.inc

Added support for initialized xilinx brams

2015-04-06 17:07:10 +02:00

synth_xilinx.cc

Added Xilinx bram black-box modules

2015-04-06 08:44:30 +02:00