mirror of https://github.com/YosysHQ/yosys.git
25 lines
504 B
Systemverilog
25 lines
504 B
Systemverilog
module top (
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input logic clk,
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input logic [1:0][5:0] in_data,
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output logic [1:0][5:0] out_data
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);
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(* nomem2reg *)
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logic my_array [1:0][5:0];
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always_ff @(posedge clk) begin
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j <= 5; j++) begin
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my_array[i][j] <= in_data[i][j];
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end
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end
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end
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always_comb begin
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j <= 5; j++) begin
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out_data[i][j] = my_array[i][j];
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end
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end
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end
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endmodule
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