yosys/frontends
Zachary Snow aa9bfdea88
Merge 51a377be44 into a54bca5493
2026-04-09 18:14:57 +00:00
..
aiger yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
aiger2 Enable xaiger2 pass when not in NDEBUG 2025-11-21 14:23:32 -08:00
ast Merge 51a377be44 into a54bca5493 2026-04-09 18:14:57 +00:00
blif blifparse: add bounds check 2026-02-11 12:16:02 +01:00
json Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00
liberty fixup! read_liberty: model clear_preset_variable correctly 2026-03-06 14:24:18 +01:00
rpc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
rtlil Work around `std::reverse` miscompilation with empty range 2026-03-06 02:03:21 +00:00
verific Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. 2026-02-02 15:26:03 -08:00
verilog support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00