georgerennie c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend

2020-12-01 01:37:19 +00:00

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aiger

Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().

2020-06-19 15:48:58 +00:00

ast

Merge pull request #2378 from udif/pr_dollar_high_low

2020-10-01 18:17:36 +02:00

blif

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

json

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

liberty

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

rpc

Fix argument handling in connect_rpc

2020-10-19 13:40:57 +02:00

rtlil

rtlil: remove dotted identifiers.

2020-11-25 16:47:20 +00:00

verific

Update verific version

2020-10-30 08:32:59 +01:00

verilog

Fix SYNTHESIS always being defined in Verilog frontend

2020-12-01 01:37:19 +00:00