mirror of https://github.com/YosysHQ/yosys.git
22 lines
390 B
Systemverilog
22 lines
390 B
Systemverilog
module top (
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input logic clk,
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input logic [3:1][2:0] in_data,
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output logic [3:1][2:0] out_data
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);
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(* nomem2reg *)
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logic [2:0] my_array [3:1];
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always_ff @(posedge clk) begin
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for (int i = 1; i <= 3; i++) begin
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my_array[i] <= in_data[i];
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end
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end
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always_comb begin
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for (int i = 1; i <= 3; i++) begin
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out_data[i] = my_array[i];
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end
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end
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endmodule
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