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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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a91892bba422bbe8de080a105a6fb4b44f96df1a
yosys/techlibs
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whitequark a91892bba4 cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
..
achronix
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
anlogic
anlogic: add latch cells
2018-12-25 22:47:46 +08:00
common
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
coolrunner2
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
easic
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ecp5
Fix 7 instances of add_share_file to add_gen_share_file
2018-12-29 12:53:12 +01:00
gowin
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
greenpak4
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
ice40
Rename "fine:" label to "map:" in "synth_ice40"
2018-12-16 16:36:19 +01:00
intel
Changes in GoWin synth commands and ALU primitive support
2018-12-03 20:08:35 -06:00
sf2
Fix sf2 LUT interface
2018-10-31 15:36:53 +01:00
xilinx
Add support for Xilinx PS7 block
2018-11-10 12:45:07 -08:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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