yosys/techlibs/xilinx
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
..
tests
.gitignore
Makefile.inc
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
cells_xtra.py move attributes to wires 2019-08-13 19:36:59 +00:00
cells_xtra.v move attributes to wires 2019-08-13 19:36:59 +00:00
ff_map.v
lut_map.v
lutrams.txt
lutrams_map.v
mux_map.v
synth_xilinx.cc Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
xc6s_brams.txt
xc6s_brams_bb.v move attributes to wires 2019-08-13 19:36:59 +00:00
xc6s_brams_map.v RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
xc7_brams.txt
xc7_brams_bb.v move attributes to wires 2019-08-13 19:36:59 +00:00
xc7_brams_map.v