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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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a58571d0fe8971cb7d3a619a31b2c21be6d75bac
yosys/techlibs
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History
Stefan Riesenberger a58571d0fe sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
..
achronix
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
anlogic
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
common
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
coolrunner2
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
easic
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
ecp5
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
efinix
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
gowin
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
greenpak4
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
ice40
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
intel
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
intel_alm
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
machxo2
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
nexus
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
quicklogic
quicklogic: PolarPro 3 support
2021-03-18 13:28:16 +01:00
sf2
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
xilinx
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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