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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 18:01:44 +02:00
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a582b9d1849a9cb1f13323d8894de3fdb0bc6c90
yosys/techlibs/common
T
History
Clifford Wolf c69c416d28 Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
..
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Makefile.inc
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
simcells.v
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
simlib.v
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
stdcells.v
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
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