This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-29 09:30:28 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
a5764a12365073768edb822e893aa9c0a957e585
yosys
/
tests
/
arch
T
History
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
..
anlogic
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
common
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
ecp5
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
efinix
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
gowin
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
ice40
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
xilinx
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
