Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
a5764a12365073768edb822e893aa9c0a957e585
yosys/techlibs
T
History
Eddie Hung c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches
2019-12-13 08:59:17 -08:00
..
achronix
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
anlogic
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
common
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
2019-11-11 15:07:29 +01:00
coolrunner2
coolrunner2: remove spurious log_pop() call, fixes #1463
2019-11-23 06:21:40 +01:00
easic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ecp5
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
efinix
FF should be initialized to 0
2019-10-04 13:27:10 +02:00
gowin
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
greenpak4
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ice40
ice40_opt to restore attributes/name when unwrapping
2019-12-09 14:29:29 -08:00
intel
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
sf2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
xilinx
Disable RAM16X1D match rule; carry-over from LUT4 arches
2019-12-13 08:59:17 -08:00
.gitignore
…
Powered by Gitea Version: 1.27.2 Page: 1103ms Template: 23ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API