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21 lines
525 B
Plaintext
21 lines
525 B
Plaintext
# partial module selection leaves the other modules alone
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read_verilog <<EOT
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module m1(input [1:0] a, output y); assign y = &a; endmodule
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module m2(input [1:0] a, output y); assign y = |a; endmodule
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module top(input [3:0] a, output y);
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wire [1:0] t;
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m1 i1(.a(a[1:0]), .y(t[0]));
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m2 i2(.a(a[3:2]), .y(t[1]));
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assign y = ^t;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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techmap
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abc_new -liberty openroad/cm_test_cells.lib m1
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select -assert-none m1/t:$_*_
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select -assert-count 1 m2/t:$_OR_
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select -assert-count 1 top/t:$_XOR_
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