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34 lines
815 B
Plaintext
34 lines
815 B
Plaintext
# $scopeinfo cells deleted by abc_new, kept by abc
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read_verilog <<EOT
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module sub(input [1:0] a, output y); assign y = &a; endmodule
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module top(input [3:0] a, output y);
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wire [1:0] t;
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sub s0(.a(a[1:0]), .y(t[0]));
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sub s1(.a(a[3:2]), .y(t[1]));
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assign y = ^t;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold_hier
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flatten
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design -save gold
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design -load gold_hier
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flatten -scopename
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select -assert-count 2 t:$scopeinfo
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techmap
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-count 2 t:$scopeinfo
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select -assert-none t:$_*_
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check -assert
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read_verilog openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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