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33 lines
795 B
Plaintext
33 lines
795 B
Plaintext
# two paramods of one module
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read_verilog <<EOT
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module inc #(parameter W = 4) (input [W-1:0] a, output [W-1:0] y);
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assign y = a + 1;
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endmodule
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module top(input [3:0] a, input [7:0] b, output [3:0] y, output [7:0] z);
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inc #(.W(4)) i4 (.a(a), .y(y));
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inc #(.W(8)) i8 (.a(b), .y(z));
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold_hier
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flatten
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design -save gold
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design -load gold_hier
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techmap
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-count 2 top/t:$paramod*
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select -assert-none t:$_*_
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opt_clean
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check -assert
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read_verilog openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert -ignore_gold_x gold gate miter
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sat -verify -prove-asserts -show-ports miter
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