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34 lines
1022 B
Plaintext
34 lines
1022 B
Plaintext
# https://github.com/librelane/librelane/blob/f24e0ea5db2260719e9a0c7d51d07db74a87fa23/librelane/scripts/pyosys/synthesize.py
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# -constr and -D; -D only reaches abc through {D} in the script
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read_verilog <<EOT
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module top(input [5:0] a, b, output [11:0] y);
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assign y = a * b;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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design -save gold
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techmap
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opt
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logger -expect log "read_constr -v abc.constr" 1
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logger -expect log "&nf -D 1234" 2
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# ABC only supports these two:
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# https://github.com/YosysHQ/abc/blob/28d955ca97a1c4be3aed4062aec0241a734fac5d/src/map/scl/sclUtil.c#L257
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abc_new -liberty ../openroad/cm_test_cells.lib -constr abc.constr -D 1234 -script +&st;&dch,-r;&nf,{D};&st;&syn2;&if,-g,-K,6;&synch2,-r;&nf,{D}
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logger -check-expected
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select -assert-none t:$_*_
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check -assert
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read_verilog ../openroad/cells_sim.v
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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miter -equiv -flatten -make_assert gold gate miter
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sat -verify -prove-asserts -show-ports miter
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