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21 lines
469 B
Plaintext
21 lines
469 B
Plaintext
# init values on flop outputs survive
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read_verilog <<EOT
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module top(input clk, a, output y);
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reg q = 1'b1;
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reg [1:0] r = 2'b10;
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always @(posedge clk) begin q <= a ^ q; r <= r + {1'b0, q}; end
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assign y = q & ^r;
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endmodule
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EOT
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hierarchy -top top
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proc
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opt
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techmap
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select -assert-count 2 a:init
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-count 1 w:q a:init %i
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select -assert-count 1 w:r a:init %i
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select -assert-none t:$_*_ t:$_DFF_P_ %d
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check -assert
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