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18 lines
476 B
Plaintext
18 lines
476 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/4977
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# abc names the duplicated cell before it asserts, which used to be lost in a
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# stdio buffer that the abort never flushed
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logger -expect log "There are two standard cells with the same name" 1
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logger -expect error "ABC" 1
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read_verilog <<EOT
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module top(input a, b, output y);
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assign y = ~(a & b);
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endmodule
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EOT
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hierarchy -top top
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techmap
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libcache -scl -disable
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abc_new -liberty openroad/cm_test_cells.lib -liberty dup_inv.lib
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