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21 lines
872 B
Plaintext
21 lines
872 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/6179
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# wrapcell abc9_box operator module ("cannot find existing box cell $box0")
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read_liberty -overwrite -setattr liberty_cell -lib ../liberty/normal.lib
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read_liberty -overwrite -setattr liberty_cell -unit_delay -wb -ignore_miss_func -ignore_buses ../liberty/normal.lib
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read_verilog <<EOT
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module tiny(input clk, input [15:0] a, b, output reg [15:0] y);
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always @(posedge clk) y <= a + b;
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endmodule
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EOT
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synth -flatten -top tiny -run :fine
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techmap -dont_map $alu
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wrapcell -setattr arithmetic_operator -name ALU_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}{%unused}_HAN_CARLSON t:$alu
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techmap -map +/techmap.v -map +/choices/han-carlson.v A:arithmetic_operator
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setattr -mod -set abc9_box 1 A:arithmetic_operator
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techmap
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abc_new -liberty ../liberty/normal.lib
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select -assert-count 1 tiny/t:ALU_*
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select -assert-none tiny/t:$_*_ tiny/t:$_DFF_P_ %d
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