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42 lines
998 B
Plaintext
42 lines
998 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/5445
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# preset-only inverted-storage flop through dfflibmap and abc_new
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read_liberty -lib -unit_delay bug5445.lib
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read_verilog <<EOT
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module top(input clk, input resetn, input a, output reg r, output y);
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always @(posedge clk or negedge resetn) begin
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if (!resetn) r <= 1'b1;
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else r <= a;
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end
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assign y = r ^ a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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synth -run fine:
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dfflibmap -liberty bug5445.lib
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select -assert-count 1 t:DFFRQN
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abc_new -liberty openroad/cm_test_cells.lib -liberty bug5445.lib
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select -assert-none t:$_*_
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check -assert
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read_verilog <<EOT
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module DFFRQN(input CK, D, RN, output reg QN);
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always @(posedge CK, negedge RN) if (!RN) QN <= 1'b1; else QN <= !D;
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endmodule
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EOT
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read_verilog openroad/cells_sim.v
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proc
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flatten
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opt_clean
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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async2sync
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equiv_make gold gate equiv
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equiv_simple -seq 5
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equiv_induct -seq 5
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equiv_status -assert
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