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21 lines
389 B
Plaintext
21 lines
389 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/5223
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# two blackboxes driving one net via inout
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read_verilog <<EOT
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(* blackbox *)
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module foo(inout x);
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endmodule
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module top(input a, output y);
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wire w;
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foo a1(.x(w));
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foo b1(.x(w));
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assign y = a & w;
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endmodule
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EOT
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hierarchy -top top
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techmap
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-count 2 t:foo
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select -assert-none t:$_*_
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