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19 lines
528 B
Plaintext
19 lines
528 B
Plaintext
# https://github.com/YosysHQ/yosys/issues/4291
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# async-set reg driving an inout bit ("visited AIG node more than once")
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read_verilog <<EOT
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module top(inout [11:0] GPIO, input _0_, input _1_, input _2_);
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reg \GPIO_reg[1] ;
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always @(posedge _0_, posedge _1_)
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if (_1_) \GPIO_reg[1] <= 1'b1;
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else \GPIO_reg[1] <= _2_;
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assign GPIO[1] = \GPIO_reg[1] ;
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endmodule
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EOT
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synth -top top -run :fine
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techmap
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abc_new -liberty openroad/cm_test_cells.lib
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select -assert-count 1 t:$_DFF_PP1_
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select -assert-none t:$_*_ t:$_DFF_PP1_ %d
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