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yosys/techlibs/quicklogic/qlf_k6n10f
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Miodrag Milanovic a689342207 Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
..
.gitignore
quicklogic: Generate bram_types_sim.v at build time
2023-12-04 18:21:00 +01:00
arith_map.v
End of file fix
2026-06-23 07:23:41 +02:00
brams_map.v
End of file fix
2026-06-23 07:23:41 +02:00
brams_sim.v
End of file fix
2026-06-23 07:23:41 +02:00
cells_sim.v
End of file fix
2026-06-23 07:23:41 +02:00
dsp_final_map.v
End of file fix
2026-06-23 07:23:41 +02:00
dsp_map.v
ql_k6n10f: Remove support for parameter-configured DSP variety
2023-12-04 15:52:02 +01:00
dsp_sim.v
ql_k6n10f: Remove support for parameter-configured DSP variety
2023-12-04 15:52:02 +01:00
ffs_map.v
End of file fix
2026-06-23 07:23:41 +02:00
generate_bram_types_sim.py
Drop timestamp in generate_bram_types_sim.py
2024-10-30 08:47:18 +01:00
libmap_brams_map.v
Remove trailing whitespaces
2026-06-23 07:24:59 +02:00
libmap_brams.txt
add qlf_k6n10f architecture + bram inference
2023-12-04 15:52:02 +01:00
sram1024x18_mem.v
End of file fix
2026-06-23 07:23:41 +02:00
TDP18K_FIFO.v
add example memory test
2023-12-04 15:52:03 +01:00
ufifo_ctl.v
add example memory test
2023-12-04 15:52:03 +01:00