Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
a4cfd1237ff92764cea121f7025fc9f9dd07462f
yosys/passes
T
History
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
..
cmds
autoname: do not autoname ports
2020-01-14 10:13:29 -08:00
equiv
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:43:43 +01:00
fsm
Update fsm_detect bugfix
2019-11-12 17:31:30 +01:00
hierarchy
Remove submod changes
2019-12-30 14:56:14 -08:00
memory
Cleanup
2019-12-17 00:25:08 -08:00
opt
Fix opt_expr.eqneq.cmpzero debug print
2019-12-15 20:40:38 +01:00
pmgen
xilinx_dsp: another typo; move xilinx specific test
2020-01-17 17:07:03 -08:00
proc
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
2019-11-21 20:46:41 +00:00
sat
Fix sim for assignments with lhs<rhs size, fixes #1565
2019-12-17 17:36:30 +01:00
techmap
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
tests
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00
Powered by Gitea Version: 1.27.2 Page: 2172ms Template: 91ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API