Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 12:21:16 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
a48ec49017a8a792841cf486167c643db23eeb22
yosys/passes
T
History
Clifford Wolf 590e6961cb Add clk2fflogic memory support
2017-12-14 02:07:31 +01:00
..
cmds
Add support for editline as replacement for readline
2017-11-08 02:55:00 +01:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Remove some dead code from fsm_map
2017-08-21 15:02:16 +02:00
hierarchy
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
proc
Add warnings for driver-driver conflicts between FFs (and other cells) and constants
2017-12-12 17:13:27 +01:00
sat
Add clk2fflogic memory support
2017-12-14 02:07:31 +01:00
techmap
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Powered by Gitea Version: 1.27.2 Page: 989ms Template: 67ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API