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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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a4238637acc4e6670ccefb1894b00c602a827408
yosys/techlibs
T
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Eddie Hung a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
This reverts commit 234738b103.
2019-09-25 17:25:44 -07:00
..
achronix
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
anlogic
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
common
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
2019-09-25 17:25:44 -07:00
coolrunner2
Fix spacing
2019-08-06 16:47:55 -07:00
easic
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ecp5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
efinix
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
gowin
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
greenpak4
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
ice40
Only wreduce on t:$add
2019-09-25 17:22:04 -07:00
intel
techlibs/intel: Clean up Makefile
2019-08-05 11:22:11 -07:00
sf2
Revert "synth_* with -retime option now calls abc with -D 1 as well"
2019-04-18 07:59:16 -07:00
xilinx
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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