yosys/techlibs/quicklogic at a3b8609c84e84d0eb3dcee26a2a4b770bbd3c8a0 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00

Files

T

History

nella a3b8609c84 Add -nolatches check option.

2026-06-24 10:38:10 +02:00

..

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

Drop timestamp in generate_bram_types_sim.py

2024-10-30 08:47:18 +01:00

CMakeLists.txt

Migrate build system to CMake

2026-06-03 08:58:10 +00:00

ql_bram_merge.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_bram_types.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_io_regs.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_dsp_macc.cc

Fixing couple more conversion errors

2026-05-14 15:58:58 +02:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ql_ioff.cc

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

synth_quicklogic.cc

Add -nolatches check option.

2026-06-24 10:38:10 +02:00