YRabbit a1dd794ff8 gowin: Add all the primitives. ...

Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <[email protected]>

2023-04-22 17:10:53 +10:00

..

achronix

Test fixes for latest iverilog

2022-09-21 15:46:43 +02:00

anlogic

anlogic: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

common

Add bitwise $bweqx and $bwmux cells

2022-11-30 18:24:35 +01:00

coolrunner2

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

easic

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ecp5

ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model

2023-04-06 10:18:48 +01:00

efinix

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous

fabulous: Add support for LUT6s

2023-04-12 18:42:09 +02:00

gatemate

gatemate: Enable register initialization

2023-02-15 17:29:01 +01:00

gowin

gowin: Add all the primitives.

2023-04-22 17:10:53 +10:00

greenpak4

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ice40

ice40: Fix path delay definitions

2023-03-10 10:48:05 +01:00

intel

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

intel_alm

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

machxo2

Add PLL and EBR related primitives

2023-04-10 12:39:09 +02:00

nexus

nexus: Fix BRAM write enable in PDP mode

2023-01-04 17:59:36 +01:00

quicklogic

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

sf2

Test fixes for latest iverilog

2022-09-21 15:46:43 +02:00

xilinx

Update Xilinx cell definitions, fixes #3699

2023-03-23 09:44:36 +01:00

.gitignore

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