mirror of https://github.com/YosysHQ/yosys.git
13 lines
339 B
Systemverilog
13 lines
339 B
Systemverilog
// Simple mux-based register -- no VPS pattern, opt_vps should not fire.
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module opt_vps_no_match (
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input logic clk,
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input logic sel,
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input logic [7:0] a, b,
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output logic [7:0] q
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);
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logic [7:0] reg_data;
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always_ff @(posedge clk)
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reg_data <= sel ? a : b;
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assign q = reg_data;
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endmodule
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