mirror of https://github.com/YosysHQ/yosys.git
950 lines
19 KiB
Plaintext
950 lines
19 KiB
Plaintext
###################################################################
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# Extract Reduce AND Gates Tests
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###################################################################
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log -header "Simple AND chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] & a[1] & a[2] & a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "AND chain with constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] a,
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output wire x
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);
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assign x = a[0] & a[1] & a[2] & 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "AND chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w0, w1, w2, w3;
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assign w0 = a[0] & a[1];
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assign w1 = a[2] & a[3];
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assign w2 = a[4] & a[5];
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assign w3 = w0 & w1;
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assign x = w2 & w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$and
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select -assert-count 1 t:$reduce_and
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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design -reset
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log -pop
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log -header "No off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] & a[1];
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assign w1 = w0 & a[2];
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assign w2 = w1 & a[3];
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assign x = w2 & a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] & a[1];
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assign w1 = w0 & a[2];
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assign w2 = w1 & a[3];
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assign x = w2 & a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_and r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=3 %i
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design -reset
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log -pop
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log -header "No off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_and r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] & a[1] & a[2] & (a[3] & a[4]) & a[5];
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assign x = w0 & a[6] & a[7] & (a[8] & a[9]) & a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_and
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_and r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce OR Gates Tests
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###################################################################
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log -header "Simple OR chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "OR chain with constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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select -assert-count 1 t:$reduce_or r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "OR chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w0, w1, w2, w3;
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assign w0 = a[0] | a[1];
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assign w1 = a[2] | a[3];
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assign w2 = a[4] | a[5];
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assign w3 = w0 | w1;
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assign x = w2 | w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$or
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select -assert-count 1 t:$reduce_or
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select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
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design -reset
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log -pop
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log -header "No off-chain OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] | a[1];
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assign w1 = w0 | a[2];
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assign w2 = w1 | a[3];
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assign x = w2 | a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 2 t:$reduce_or
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# Check that both gates are 3 bits wide
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select -assert-none t:$reduce_or r:A_WIDTH!=3 %i
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design -reset
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log -pop
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log -header "Allow off-chain for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x,
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output wire y
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);
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wire w0, w1, w2;
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assign w0 = a[0] | a[1];
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assign w1 = w0 | a[2];
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assign w2 = w1 | a[3];
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assign x = w2 | a[4];
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// Off-chain use of w1
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assign y = w1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 2 t:$reduce_or
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# Check that only one gate has a width of 5 and one gate has a width of 3
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select -assert-count 1 t:$reduce_or r:A_WIDTH=5 %i
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select -assert-count 1 t:$reduce_or r:A_WIDTH=3 %i
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design -reset
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log -pop
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log -header "No off-chain with branches for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
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assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$and
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select -assert-count 2 t:$reduce_or
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# Check that both gates are 6 bits wide
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select -assert-none t:$reduce_or r:A_WIDTH!=6 %i
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design -reset
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log -pop
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log -header "Allow off-chain with branches for OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [10:0] a,
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output wire x,
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output wire y
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);
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wire w0;
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assign w0 = a[0] | a[1] | a[2] | (a[3] | a[4]) | a[5];
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assign x = w0 | a[6] | a[7] | (a[8] | a[9]) | a[10];
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// Off-chain use of w0
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assign y = w0;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce -allow-off-chain
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates
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select -assert-count 0 t:$or
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select -assert-count 2 t:$reduce_or
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# Check that only one gate has a width of 11 and one gate has a width of 6
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select -assert-count 1 t:$reduce_or r:A_WIDTH=11 %i
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select -assert-count 1 t:$reduce_or r:A_WIDTH=6 %i
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design -reset
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log -pop
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###################################################################
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# Extract Reduce XOR Gates Tests
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###################################################################
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log -header "Simple XOR chain"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] ^ a[1] ^ a[2] ^ a[3];
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$xor
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select -assert-count 1 t:$reduce_xor
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "XOR chain with constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] ^ a[1] ^ a[2] ^ 1'b1;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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select -assert-count 0 t:$xor
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select -assert-count 1 t:$reduce_xor
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select -assert-count 1 t:$reduce_xor r:A_WIDTH=4 %i
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design -reset
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log -pop
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log -header "XOR chain with multiple branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] a,
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output wire x
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);
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wire w0, w1, w2, w3;
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assign w0 = a[0] ^ a[1];
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assign w1 = a[2] ^ a[3];
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assign w2 = a[4] ^ a[5];
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assign w3 = w0 ^ w1;
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assign x = w2 ^ w3;
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endmodule
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EOF
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check -assert
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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# Check final design has correct number of gates and inputs
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|
select -assert-count 0 t:$xor
|
|
select -assert-count 1 t:$reduce_xor
|
|
select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "No off-chain XOR"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [4:0] a,
|
|
output wire x,
|
|
output wire y
|
|
);
|
|
wire w0, w1, w2;
|
|
|
|
assign w0 = a[0] ^ a[1];
|
|
assign w1 = w0 ^ a[2];
|
|
assign w2 = w1 ^ a[3];
|
|
assign x = w2 ^ a[4];
|
|
|
|
// Off-chain use of w1
|
|
assign y = w1;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates
|
|
select -assert-count 0 t:$xor
|
|
select -assert-count 2 t:$reduce_xor
|
|
|
|
# Check that both gates are 3 bits wide
|
|
select -assert-none t:$reduce_xor r:A_WIDTH!=3 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Allow off-chain for XOR"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [4:0] a,
|
|
output wire x,
|
|
output wire y
|
|
);
|
|
wire w0, w1, w2;
|
|
|
|
assign w0 = a[0] ^ a[1];
|
|
assign w1 = w0 ^ a[2];
|
|
assign w2 = w1 ^ a[3];
|
|
assign x = w2 ^ a[4];
|
|
|
|
// Off-chain use of w1
|
|
assign y = w1;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce -allow-off-chain
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates
|
|
select -assert-count 0 t:$xor
|
|
select -assert-count 2 t:$reduce_xor
|
|
|
|
# Check that only one gate has a width of 5 and one gate has a width of 3
|
|
select -assert-count 1 t:$reduce_xor r:A_WIDTH=5 %i
|
|
select -assert-count 1 t:$reduce_xor r:A_WIDTH=3 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "No off-chain with branches for XOR"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [10:0] a,
|
|
output wire x,
|
|
output wire y
|
|
);
|
|
wire w0;
|
|
|
|
assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
|
|
assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
|
|
|
|
// Off-chain use of w0
|
|
assign y = w0;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates
|
|
select -assert-count 0 t:$xor
|
|
select -assert-count 2 t:$reduce_xor
|
|
|
|
# Check that both gates are 6 bits wide
|
|
select -assert-none t:$reduce_xor r:A_WIDTH!=6 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Allow off-chain with branches for XOR"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [10:0] a,
|
|
output wire x,
|
|
output wire y
|
|
);
|
|
wire w0;
|
|
|
|
assign w0 = a[0] ^ a[1] ^ a[2] ^ (a[3] ^ a[4]) ^ a[5];
|
|
assign x = w0 ^ a[6] ^ a[7] ^ (a[8] ^ a[9]) ^ a[10];
|
|
|
|
// Off-chain use of w0
|
|
assign y = w0;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce -allow-off-chain
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates
|
|
select -assert-count 0 t:$xor
|
|
select -assert-count 2 t:$reduce_xor
|
|
|
|
# Check that only one gate has a width of 11 and one gate has a width of 6
|
|
select -assert-count 1 t:$reduce_xor r:A_WIDTH=11 %i
|
|
select -assert-count 1 t:$reduce_xor r:A_WIDTH=6 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
###################################################################
|
|
# Edge Cases
|
|
###################################################################
|
|
|
|
log -header "Reconvergence"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a,
|
|
output wire y
|
|
);
|
|
wire w0, w1, w2, w3, w4, w5, w6;
|
|
|
|
assign w0 = a[0] & a[1];
|
|
assign w1 = a[2] & a[3];
|
|
assign w2 = w0 & w1;
|
|
assign w3 = w2 & a[4];
|
|
assign w4 = w2 & a[5];
|
|
assign w5 = w3 & a[6];
|
|
assign w6 = w4 & a[7];
|
|
assign y = w5 & w6;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates and inputs
|
|
select -assert-count 0 t:$and
|
|
select -assert-count 2 t:$reduce_and
|
|
select -assert-count 1 t:$reduce_and r:A_WIDTH=4 %i
|
|
select -assert-count 1 t:$reduce_and r:A_WIDTH=6 %i
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Stress test"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a0,
|
|
input wire [7:0] a1,
|
|
input wire [7:0] a2,
|
|
output wire y
|
|
);
|
|
wire c0, c1, c2;
|
|
|
|
// Stage 0
|
|
wire s0_w0 = a0[0] & a0[1];
|
|
wire s0_w1 = a0[2] & a0[3];
|
|
wire s0_w2 = s0_w0 & s0_w1;
|
|
wire s0_w3 = s0_w2 & a0[4];
|
|
wire s0_w4 = a0[0] & a0[5];
|
|
wire s0_w5 = s0_w3 & a0[6];
|
|
wire s0_w6 = s0_w4 & a0[7];
|
|
assign c0 = s0_w5 & s0_w6;
|
|
|
|
// Stage 1
|
|
wire s1_w0 = a1[0] & a1[1];
|
|
wire s1_w1 = a1[2] & a1[3];
|
|
wire s1_w2 = s1_w0 & s1_w1;
|
|
wire s1_w3 = s1_w2 & a1[4];
|
|
wire s1_w4 = c0 & a1[5];
|
|
wire s1_w5 = s1_w3 & a1[6];
|
|
wire s1_w6 = s1_w4 & a1[7];
|
|
assign c1 = s1_w5 & s1_w6;
|
|
|
|
// Stage 2
|
|
wire s2_w0 = a2[0] & a2[1];
|
|
wire s2_w1 = a2[2] & a2[3];
|
|
wire s2_w2 = s2_w0 & s2_w1;
|
|
wire s2_w3 = s2_w2 & a2[4];
|
|
wire s2_w4 = c1 & a2[5];
|
|
wire s2_w5 = s2_w3 & a2[6];
|
|
wire s2_w6 = s2_w4 & a2[7];
|
|
assign c2 = s2_w5 & s2_w6;
|
|
|
|
assign y = c2;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
extract_reduce
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates and inputs
|
|
select -assert-count 0 t:$and
|
|
select -assert-count 1 t:$reduce_and
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Stress test reconvergence"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a0,
|
|
input wire [7:0] a1,
|
|
input wire [7:0] a2,
|
|
output wire y
|
|
);
|
|
wire c0, c1, c2;
|
|
|
|
// Stage 0
|
|
wire s0_w0 = a0[0] & a0[1];
|
|
wire s0_w1 = a0[2] & a0[3];
|
|
wire s0_w2 = s0_w0 & s0_w1;
|
|
wire s0_w3 = s0_w2 & a0[4];
|
|
wire s0_w4 = s0_w2 & a0[5];
|
|
wire s0_w5 = s0_w3 & a0[6];
|
|
wire s0_w6 = s0_w4 & a0[7];
|
|
assign c0 = s0_w5 & s0_w6;
|
|
|
|
// Stage 1
|
|
wire s1_w0 = a1[0] & a1[1];
|
|
wire s1_w1 = a1[2] & a1[3];
|
|
wire s1_w2 = s1_w0 & s1_w1;
|
|
wire s1_w3 = s1_w2 & a1[4];
|
|
wire s1_w4 = s1_w2 & a1[5];
|
|
wire s1_w5 = s1_w3 & a1[6];
|
|
wire s1_w6 = s1_w4 & c0;
|
|
assign c1 = s1_w5 & s1_w6;
|
|
|
|
// Stage 2
|
|
wire s2_w0 = a2[0] & a2[1];
|
|
wire s2_w1 = a2[2] & a2[3];
|
|
wire s2_w2 = s2_w0 & s2_w1;
|
|
wire s2_w3 = s2_w2 & a2[4];
|
|
wire s2_w4 = s2_w2 & a2[5];
|
|
wire s2_w5 = s2_w3 & a2[6];
|
|
wire s2_w6 = s2_w4 & c1;
|
|
assign c2 = s2_w5 & s2_w6;
|
|
|
|
assign y = c2;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after extract_reduce
|
|
equiv_opt -assert extract_reduce
|
|
|
|
# Load design and run opt_clean to remove unnecessary wires
|
|
design -load postopt
|
|
opt_clean
|
|
|
|
# Check final design has correct number of gates and inputs
|
|
select -assert-count 0 t:$and
|
|
select -assert-count 4 t:$reduce_and
|
|
|
|
design -reset
|
|
log -pop |