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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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a179d918ec4e5ed595e8f556b159ab39679d4e6c
yosys/techlibs/ice40
T
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Eddie Hung 6bd9550100 ice40: add delays to SB_CARRY
2020-02-27 10:17:29 -08:00
..
tests
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
.gitignore
…
abc9_model.v
ice40: specify fixes
2020-02-27 10:17:29 -08:00
arith_map.v
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
brams_init.py
…
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
brams.txt
…
cells_map.v
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
cells_sim.v
ice40: add delays to SB_CARRY
2020-02-27 10:17:29 -08:00
dsp_map.v
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
ice40_braminit.cc
substr() -> compare()
2019-08-07 12:20:08 -07:00
ice40_ffinit.cc
ice40: Demote conflicting FF init values to a warning
2019-12-31 02:38:10 +01:00
ice40_ffssr.cc
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-08 22:46:28 +01:00
ice40_opt.cc
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
2020-01-27 14:02:13 -08:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
ice40: move over to specify blocks for -abc9
2020-02-27 10:17:29 -08:00
synth_ice40.cc
ice40: specify fixes
2020-02-27 10:17:29 -08:00
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