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yosys/backends/firrtl
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Adam Izraelevitz 794cec0016 More progress on Firrtl backend. 
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
 		2017-02-13 11:17:53 -08:00
..
.gitignore Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00
Makefile.inc Added first draft of FIRRTL back-end 2016-11-17 23:36:47 +01:00
firrtl.cc More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
test.sh More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00
test.v More progress on Firrtl backend. 2017-02-13 11:17:53 -08:00