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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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a051801b72c7d526a1c04cf2635ae8d7fe43a135
yosys/techlibs/intel
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History
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
..
arria10gx
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
common
intel: Map M9K BRAM only on families that have it
2019-07-23 18:11:11 +01:00
cyclone10lp
synth_intel: cyclone10 -> cyclone10lp
2019-12-10 13:47:58 +00:00
cycloneiv
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
cycloneive
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
cyclonev
Fixing issues in CycloneV cell sim
2019-04-11 19:59:03 -05:00
max10
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Makefile.inc
synth_intel: a10gx -> arria10gx
2019-12-10 13:48:10 +00:00
synth_intel.cc
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
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