This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-10-06 10:03:36 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
9f7040b3d1147641fd05e41a051c26ee8d0193dd
yosys
/
techlibs
/
quicklogic
/
common
T
History
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00