yosys/backends at 9f1c445fbf0435779a79e985fa11bb26bc0d626a - yosys - Gitea: Git with a cup of tea

luke/yosys

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Martin Povišer 18d1907fa8 cxxrtl: Assert well-formedness of input to udivmod

2023-12-12 10:08:12 +01:00

..

Merge pull request #3778 from jix/yw_clk2fflogic

2023-06-05 16:15:04 +02:00

Slightly adjust the wording of "write_blif" help

2023-07-10 12:41:43 +02:00

Use clk2fflogic attr on cells to track original FF names in witnesses

2023-05-25 12:48:02 +02:00

cxxrtl: Assert well-formedness of input to udivmod

2023-12-12 10:08:12 +01:00

Improve EDIF lib_cell_ports scan

2023-06-20 10:42:05 +02:00

Mention 'bwmuxmap' in 'write_firrtl' help

2023-07-10 12:45:03 +02:00

Intersynth URL

2021-06-09 12:42:52 +02:00

Drop stray 'cellaigs.h' include from backend passes

2023-07-10 12:45:03 +02:00

Fixes for some of clang scan-build detected issues

2023-01-17 12:58:08 +01:00

backends/rtlil: Do not shorten a value with z bits to 'x

2023-01-29 14:02:25 +01:00

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

smtbmc: Add --incremental mode

2023-11-16 13:22:17 +01:00

Add bwmuxmap pass

2022-11-30 18:50:53 +01:00

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

write_verilog: avoid emitting empty cases.

2023-10-08 01:11:30 +02:00